To acquire a high-performance large scale integrated circuit (LSI), copper has recently been used as a wiring material. As copper has a lower resistance than that of aluminum, a fast circuit is provided. As copper has a high diffusibility, however, copper, if in directly contact with a semiconductor, deteriorates the semiconductor characteristics.
Due to the high diffusibility, unlike aluminum wires, copper wires cannot be formed by an etching process. Therefore, a so-called dual damascene scheme is used as a method of forming copper multilayer wiring without etching.
The following describes steps of fabricating a semiconductor device having copper multilayer wiring using the dual damascene scheme with reference to FIGS. 10A to 10D. First, a cap layer 103 of silicon nitride or the like is formed on a first insulating layer 102 of silicon oxide or the like in which an underlying wiring layer 101 is buried. The underlying wiring layer 101 comprises a conductive layer 104 of copper or the like and a barrier layer 105 of tantalum nitride or the like which encloses the conductive layer 104.
Next, a second insulating layer 106 of silicon oxide or the like is formed on the cap layer 103. The cap layer 103 prevents diffusion of copper to the second insulating layer 106 from the underlying wiring layer 101. Further, a stopper layer 107 of silicon nitride or the like is formed on the second insulating layer 106, and a third insulating layer 108 of silicon oxide or the like is deposited on the stopper layer 107. This provides a resultant structure as shown in FIG. 10A.
Subsequently, as shown in FIG. 10B, a first photoresist pattern 109 is formed on the third insulating layer 108 and a hole 110 with the conductive layer 104 as its bottom is formed by etching. At this time, etching is carried out under the conditions where the second and third insulating layers 106 and 108, the stopper layer 107 and the cap layer 103 are all etched. After etching, the first photoresist pattern 109 is removed by ashing or the like.
Then, as shown in FIG. 10C, a second photoresist pattern 111 is formed on the third insulating layer 108 and selective etching is performed. Here, etching is carried out under the conditions where the third insulating layer 108 is etched while the stopper layer 107 is not etched. That is, the stopper layer 107 serves as an etching stopper.
In etching, a trench hole 112 which overlaps the hole 110 and has the stopper layer 107 as its bottom is formed in the third insulating layer 108. As a result, the trench hole 112 and a contact hole 113 which connects the trench hole 112 to the underlying wiring layer 101 are formed. After etching, the second photoresist pattern 111 is removed by ashing or the like.
Subsequently, a barrier layer 114 of tantalum nitride or the like is formed on the inner walls of the trench hole 112 and the contact hole 113 by CVD or the like. Further, after the trench hole 112 and the contact hole 113 are buried by plating, excess metal layers are removed by CMP. Through the above-described steps, a plug layer 15 and an overlying wiring layer 116 which is connected to the underlying wiring layer 101 via the plug layer 115 are formed as shown in FIG. 10D. By repeating the above-described steps, a multi-level wiring layer having two or more layers can be formed.
The stopper layer 107 and the cap layer 103 exist in the interlayer insulating film in the semiconductor device that is formed by the dual damascene scheme. Normally, the stopper layer 107 and the cap layer 103 are comprised of insulating films of the same material, i.e., they are formed by using the same film deposition apparatus.
The insulating films that constitute the cap layer 103 and the stopper layer 107 can generally be classified into a type which essentially consists of silicon (Si) and nitrogen (N) (hereinafter referred to as SiCN-based film) and a type which essentially consists of Si and carbon (C) (hereinafter referred to as SiC film).
As the insulating films are present in the interlayer insulating film they are demanded of a low dielectric constant. Further, the insulating films are demanded of a high etching selectivity, as the stopper layer, with respect to the interlayer insulating film, and are demanded of a high barrier property against an wiring material (i.e. low metal diffusibility) as the cap layer.
In case where the insulating films are formed of an SiC film, while the dielectric constant of the film is about 5 which is relatively low and a high etching selectivity is obtained with respect to the interlayer insulating film, the barrier property against copper thereof is low. In case where the insulating films are composed of an SiCN-based film, on the other hand, while the barrier property against copper is high, the dielectric constant is about 7 to 8 which is relatively high and the etching selectivity is low. In case where FSG (Fluorinated Silicate Glass) is used for the interlayer insulating film, the SiCN-based film is likely to be damaged by fluorine radicals that are produced at the time of etching.
As apparent from the above, the insulating films that constitute the conventional stopper layer and/or cap layer did not fully satisfy all of a low dielectric constant, a high etching selectivity with respect to the interlayer insulating film and a barrier property for the wiring material, and it was hard to provide a sufficiently reliable semiconductor device.